A flash memory is a non-volatile electrically erasable data storage device that evolved from electrically erasable programmable read-only memory (EEPROM). The two main types of flash memory are named after the logic gates that their storage cells resemble: NAND and NOR. NAND flash memory is commonly used in solid-state drives, which are supplanting magnetic disk drives in many applications. A NAND flash memory is commonly organized as multiple blocks, with each block organized as multiple pages. Each page comprises multiple cells. Each cell is capable of storing an electric charge. Some cells are used for storing data bits, while other cells are used for storing error-correcting code bits. A cell configured to store a single bit is known as a single-level cell (SLC). A cell configured to store two bits is known as a multi-level cell (MLC). In an MLC cell, one bit is commonly referred to as the least-significant bit (LSB), and the other as the most-significant bit (MSB). A cell configured to store three bits is known as a triple-level cell (TLC). Writing data to a flash memory is commonly referred to as “programming” the flash memory, due to the similarity to programming an EEPROM.
The electric charge stored in a cell can be detected in the form of a cell voltage. To read an SLC flash memory cell, the flash memory controller provides one or more reference voltages (also referred to as read voltages) to the flash memory device. Detection circuitry in the flash memory device will interpret the bit as a “0” if the cell voltage is greater than a reference voltage Vref and will interpret the bit as a “1” if the cell voltage is less than the reference voltage Vref. Thus, an SLC flash memory requires a single reference voltage Vref. In contrast, an MLC flash memory requires three such reference voltages, and a TLC flash memory requires seven such reference voltages. Thus, reading data from an MLC or TLC flash memory device requires that the controller provide multiple reference voltages having optimal values that allow the memory device to correctly detect the stored data values.
Determining or detecting stored data values using controller-provided reference voltages is hampered by undesirable physical non-uniformity across cells of a device that are inevitably introduced by the fabrication process, as such non-uniformity results in the reference voltages of different cells that store the same bit value being significantly different from each other. The detection is further hampered by target or optimal reference voltages changing over time due to adverse effects of changes in temperature, interference from programming neighboring cells, and numerous erase-program cycles. Errors in detecting stored data values are reflected in the performance measurement known as bit error rate (BER). The use of error-correcting codes (ECCs) can improve BER to some extent, but the effectiveness of ECCs diminishes as improved fabrication processes result in smaller cell features.
As illustrated in FIG. 1, an MLC flash memory has four cell voltage distributions 2, 4, 6 and 8 with four respective mean target cell voltages Vtarget0 12, Vtarget1 14, Vtarget2 16 and Vtarget3 18. Such cell voltage distributions commonly overlap each other slightly, but such overlap is not shown in FIG. 1 for purposes of clarity. During a read operation, to attempt to characterize or detect the two bits of cell data (i.e., the LSB and MSB) a flash memory device (not shown) uses three reference voltages it receives from a flash memory controller (not shown): Vref0 22, Vref1 24 and Vref2 26. More specifically, the flash memory device compares the cell voltage with Vref1 24 to attempt to detect the LSB. If the flash memory device determines that the cell voltage is less than Vref1 24, i.e., within a window 28, then the flash memory device characterizes the LSB as a “1”. If the flash memory device determines that the cell voltage is greater than Vref1 24, i.e., within a window 30, then the flash memory device characterizes the LSB as a “0”.
The flash memory device also compares the cell voltage with Vref0 22 and Vref2 26 to attempt to detect the MSB. If the flash memory device determines that the cell voltage is between Vref0 22 and Vref2 26, i.e., within a window 32, then the flash memory device characterizes the MSB as a “0”. If the flash memory device determines that the cell voltage is either less than Vref0 22 or greater than Vref2 26, i.e., within a window 34, then the flash memory device characterizes the MSB as a “1”.
To improve BER beyond what is commonly achievable with hard-decoded ECCs, flash memory controllers may employ soft-decoded ECCs, such as low density parity check (LDPC) ECCs. Soft decoding is more powerful in correcting errors than hard decoding, but soft input information must be provided to the ECC decoding logic. The ECC decoder soft input information is commonly provided in the form of log likelihood ratio (LLR) information.
MLC NAND flash memory is programmed in two stages, namely, a first stage during which LSB page programming is performed, and a second stage during which MSB page programming is performed. The first stage includes the following: (1) the flash memory controller sends LSB data to flash memory; (2) the flash memory loads the LSB data into an LSB page buffer portion of the flash memory; and (3) the flash memory uses the LSB data to program the corresponding LSB page of the flash memory. The second stage includes the following: (1) the flash memory controller sends the MSB data to be programmed to flash memory; (2) the flash memory loads the MSB data into an MSB page buffer portion of the flash memory; (3) logic of the flash memory reads the LSB page of the corresponding flash cells and loads the read LSB data into the LSB page buffer portion; (4) the logic uses the MSB and LSB value pairs held in the flash page buffer to determine the target reference voltage ranges to be programmed for the corresponding flash cells; and (5) the logic programs the target reference voltage ranges into the flash memory.
As flash memory technology improves, the sizes of the flash dies scale down, which results in the distance between neighboring flash cells becoming smaller. Because of the nearness of neighboring flash cells to one another, the programming of one flash cell can affect the charges stored on nearby flash cells, which contributes to the potentially noisy and unreliable nature of flash cells. Consequently, there can be errors in the LSB page data read out of the corresponding flash cells. Because the LSB page data read out of the flash cells is used in combination with the MSB page data to determine the target reference voltage ranges for the corresponding cells, such errors will typically cause the target reference voltage ranges to be incorrectly determined. This can cause the flash cells to be mis-programmed to improper reference voltage ranges when performing MSB page programming. The improper reference voltage ranges often will be far away from the borders of flash neighbor states and could provide incorrect, but highly confident, soft information. This, in turn, can significantly degrade the error correction performance of soft decoding, such as LDPC decoding.
FIG. 2 illustrates cell voltage distributions and target reference voltage ranges for different LSB and MSB states and demonstrates the manner in which the reference voltage ranges are selected based on the values of the MSB and LSB pair. Cell voltage distribution 42 represents the LSB and MSB erased program state. Cell distributions 43 and 44 represent LSB “1” and “0” programmed states, respectively. Cell distributions 45, 46, 47, and 48 represent MSB programmed states of “1,” “0,” “0,” and “1,” respectively.
If the MSB and LSB values of the MSB, LSB pair contained in the flash page buffer are both “1,” then the reference voltage range that will be programmed into the flash memory for the corresponding flash cells is selected to be range A, which is the range of reference voltages that is less than Vref0. If the MSB and LSB values of the MSB, LSB pair contained in the flash page buffer are “1” and “0,” respectively, then the reference voltage range that will be programmed into the flash memory device for the corresponding flash cells is selected to be range D, which is the range of reference voltages that is greater than Vref2. If the MSB and LSB values of the MSB, LSB pair contained in the flash page buffer are “0” and “1,” respectively, then the reference voltage range that will be programmed into the flash memory device for the corresponding flash cells is selected to be range B, which is the range of reference voltages that is greater than Vref0 and less than Vref1.
As can be seen from the above, if the LSB values that are read from the flash cells are inaccurate, which is possible for the reasons described above, then the reference voltage ranges will likely be mis-programmed. Accordingly, a need exists for a way of ensuring that the reference voltage ranges are correctly determined and programmed.